1. Field of the Invention
The present invention relates in general to devices for testing semiconductor memories, and relates in particular to a self-diagnostic device for high-bit, high-capacity memories used in IC testers.
2. Description of the Related Art
FIG. 6 shows a conventional self-diagnostic testing device for semiconductor memories disclosed in a Japanese Patent Application, First Publication, H6-75023. The device comprises: a CPU 1; a data generation circuit 2; an address generation circuit 3; a comparator 4; a memory matrix 5; a clock generator 6; a test completion detection circuit 7; a switching circuit 8; a flip-flop generation circuit (shortened to FF circuit hereinbelow) 9; divider circuits 10.about.14; selectors 15.about.17; and an inversion circuit 18. It should be noted that, in the following description, the terms "signal" and "data" are interchangeable, and refer to a single signal or a group of signals depending on the situation.
The output signal 1B of CPU 1 is [H] for the write-mode and [L] for the read-mode. The output signal 1D is [H] for the checker-mode and [L] for the march-mode. The output signal 1C is inputted to the divider circuit 10 to divide the clock signal 6E generated by the clock generation circuit 6.
The divider circuit 11 divides the clock signal 6A generated by the clock generation circuit 6; the divider circuit 12 divides the clock signal 6B generated by the clock generation circuit 6; the divider circuit 13 divides the clock signal 6D generated by the clock generation circuit 6; and the divider circuit 14 divides the output signal generated by the divider circuit 12.
The selector 15 receives the clock signal 6A outputted from the clock generation circuit 6 and the signal 11A outputted from the divider circuit 11, and selects a clock signal 6A when the output signal 1B from CPU 1 is [H] or output signal 11A, when 1B is [L]. The selector 16 receives the output clock signals 12A, and 14A, respectively, from the divider circuits 12, 14, and selects clock signal 14A when the output signal from the AND-gate 22 is [H], or 12A when it is [L]. The selector 17 receives the inverted signal of the clock signal 6C from the clock generation circuit 6 and the output signal 23A from the gate 23, and selects the output signal 23A from the gate 23 when the output signal 1B from CPU 1 is [H] and selects clock signal 6C from the clock generation circuit 6 when 1B is [L]. The inversion circuit 18 receives output signal from the data generation circuit 2 and the output signal from the AND-gate 20, and provides input data to the switching circuit 8.
The memory matrix 5 receives output data 8A from the switching circuit 8, and accepts write-data in at the output timing of the selector 17. The comparator 4 receives output data from the memory matrix 5 and the output data 8B from the switching circuit 8, and outputs a signal 4A at the timings governed by the NAND-gate 24. The NAND-gate 24 receives output signal 13A from the divider circuit 13 and the inverted data of the output signal 1B of CPU 1.
Before testing the memory matrix 5 using the diagnostic device shown in FIG. 6, it is necessary to establish the test conditions for the various components of the device. First, a range of test addresses must be defined by providing the starting addresses to the address generation circuit 13 according to input data 1A from CPU 1. Similarly, the range of test addresses is provided to the test completion detection circuit 7 by input data 1A. Next, the conditions for testing memory matrix 5 are provided to the address generation circuit 3 and the test completion detection circuit 7. The testing sequence data are entered into the data generation circuit 2 by the input data 1A from CPU 1.
Next, the write-process for the march-mode will be explained. The march-mode refers to a step of initializing all the cells by writing [0], followed by a cell-by-cell read/write step for each one of the cells, and a step of repeating the same sequence of steps for the inverted data. This procedure assures that nearly all the fixation defects in the address system are detected.
The write process for the march-mode comprises inputting [1] or [0] in all the cells to check the writing ability. The sequence of events are as follows. After entering the write conditions as above, the selector 15 is set so as to be [H] when read- or write-mode signal 1B is [H] and checker- or march-mode signal 1D is [L]. Then, CPU 1 inputs a start signal 1C to the clock generation circuit 6 to output a clock signal 6A, and test data are entered into the address generation circuit 3, the data generation circuit 2 and the test completion detection circuit 7.
At this point, the OR-gate 19 is [L], AND-gate 22 is [L] and the selector 16 is set to [L]. The input to the AND-gate 20 (output of the OR-gate 19) is [L] and the output 12A of the divider circuit 12 through the selector 16 is [L], therefore, the output is constant at [L]. Therefore, the output signal 18A from the inversion circuit 18 passes through and is inputted to the switching circuit 8. The output 10A of the divider circuit 10 and the read- or write-mode signal 1B are entered into the OR-gate 21 to provide the output signal at [H]. Therefore, the output from the switching circuit 8 appears on the 8A-side. At this time, by giving the clock signal 6C from the clock circuit 6 to a WE (write enable) terminal, the output of the selector 17 writes test data into the memory in each address.
Next, the read steps for the march-mode in the circuit of FIG. 6 will be explained. When write- or read-mode signal 1B is [L] and checker- or march-mode signal 1D is [L], the selector 15 is set to [L]. Therefore, the output signal 11A from the divider circuit 11 is given to the address generation circuit 3, data generation circuit 2 and the test completion detection circuit 7. At this time, the output signal is [H] from the ON-gate 19, [L] from the AND-gate 22, and output signal 12A from the divider circuit 12 is generated by the selector 16.
In this circuit configuration, the output of the AND-gate 20 is provided to the input of the switching circuit 8, after the output from the divider circuit 12 has gone through the inversion circuit 18 to be subjected to repeated process of through/inversion step. When the output signal 10A from the divider circuit 10 is [H], through-data is outputted on the output 8B-side and the inverted-data is outputted on the 8A-side. When the WE-terminal of the memory matrix 5 is [L], the output from the NAND-gate 23 is forwarded to the selector 17, and the address of the inverted data in the memory matrix 5 is determined by the output of the address generation circuit 3, and this address is written into the memory matrix 5.
When the WE-terminal of the memory matrix 5 is [H], it is in the read-mode, the memory matrix 5 reads the address data from the output of the address generation circuit 3, and this address is inputted to the comparator 4. The comparator 4 compares the read-data from the memory matrix 5 with the output-data from the switching circuit 8 (while controlling the output read-data by WE-terminal), to determine coincidence or non-coincidence. When it is non-coincident, the comparator 4 outputs a non-coincidence signal 4A, which is inputted to the set-terminal of the FF circuit 9 to put the FF circuit 9 into a set-state to output a defect-signal 31.
Next, the write process in a checker board will be explained. The checker board is a device for writing alternating data of [H] and [L] in a checker board pattern to be read out and compared one-by-one. This process not only determines defective cells, but enables to check inter-cell interferences and defective multiplexing ability of the lowermost address bits. In the circuit shown in FIG. 6, when the output 1B of the write-mode of CPU 1 is [H] and the output 1D from the checker- or march-mode is [H], the selector 15 is [H], and the clock signal 6A is generated from the clock generation circuit 6 to be entered into the address generation circuit 3, data generation circuit 2 and the test completion detection circuit 7.
At this point, the OR-gate 19 is [H], the AND-gate 22 is [L], and output signals are set in the selector 16. Because the output of the OR-gate 19 is [H] and the input data is to the AND-gate 20, the output signal from the AND-gate 20 is the output 12A of the divider circuit 12. Therefore, the inverted circuit 8 outputs a signal 8A which alternately shows a through/inversion signal, and because the input signal to the OR-gate 21 is [H], the switching circuit 8 is [H], and the signal is outputted on the inverted-side 8A.
By operating the clock signal 6C from the clock generation circuit 6 on the WE-terminal of the memory matrix 5, the output data from the selector 17 are inverted and written into the memory matrix 5 as [H] [L] [H] [L] for each address.
Next, read-mode of the checker-board will be explained. When read- or write-mode signal 1B from CPU 1 is [L] and the output signal 1D of the checker- or march-mode is [H], the selector 15 is set to [L]. The output signal 11A is generated by the dlvider circuit 11 and is entered into the address generation circuit 3, data generation circuit 2 and the test completion detection circuit 7. At this point, the OR-gate 19 is [H] and the input to the AND-gate 22 is [H].
Also, the output signal 14A from the division circuit 14 is inputted to the selector 16. Therefore, the output of the AND-gate 20 is the output of the divider circuit 14 which is inputted to the inversion circuit 18. The output data repeat the process of through/inversion to be forwarded to the input of the switching circuit 8. The output signal 10A from the divider circuit 10 is inputted in the switching circuit 8, and the through-data are outputted on the 8B-side and the inverted-data are outputted on the inverted-side 8A. The subsequent steps are the same as in the march read-mode.
The selector 15 selects one of either the output signal 11A from the divider circuit 11 or the clock signal 6A from the clock generation circuit 6, and the address of the address generation circuit 3 is made to be +1 or -1, and the data in the data generation circuit 2 is made to be +1 or -1 or unchanged. Simultaneously, the test completion detection circuit 7 starts counting down according to the signal from the output of the selector 15, and when the count becomes [0], the testing is deemed to be completed. At this point, the test completion signal is generated to be inputted to the clock generation circuit 6. When the test completion signal is received, the clock generation circuit 6 stops the clock generation process.
As described in some detail above, the performance of the conventional self-diagnostic device for detecting defects in the memory matrix is basically governed by the cycle timing of the clock signals 6A, 6B, 6C, 6E and 6D generated from the clock signal generation circuit 6. The generated clock signals must be operated on further by the respective division circuits to generate individual signals for checking the memory matrices. Therefore, although the conventional device is highly effective in finding defective cells because of the provisions of the march-mode for checking the address configuration and the checker-mode for evaluating the individual cell performance, the device requires five division circuits, three selector circuits and six gates. The circuit configuration is thus complex and cumbersome, and the circuit design is unnecessary on a grand scale.